`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   02:54:38 10/05/2011
// Design Name:   CPU_FSM
// Module Name:   C:/Users/david/Desktop/16bitcpu/fsm_test.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: CPU_FSM
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module fsm_test;

	// Inputs
	reg CLK;
	reg reset;

	// Instantiate the Unit Under Test (UUT)
	CPU_FSM uut (
		.CLK(CLK), 
		.reset(reset)
	);

	initial begin
		// Initialize Inputs
		CLK = 0;
		reset = 0;

		// Wait 100 ns for global reset to finish
		#100;
		reset=1;
		#100
		reset=0;
        
		// Add stimulus here

	end
      always begin
		#20 CLK=~CLK;
		end
endmodule

